1. Field of the Invention
The present invention relates to a semiconductor memory device and, more particularly, to a dynamic random access memory (DRAM) and a method for screening the same.
2. Description of the Related Art
A screening process is generally performed to expose latent defects in semiconductor devices and remove from finished batches those devices having defects. This screening process prevents defect-free devices from being adversely affected by defective devices and ensures the reliability of the finished semiconductor devices before and after they are put on the market. According to one screening method, semiconductor devices are operated using a voltage higher than the actual working voltage, and voltage stress is applied to the semiconductor devices for a period of time longer than the initial failure period under actual working conditions. The semiconductor devices are then screened and those which are considered likely to malfunction in initial operation are removed. This type of screening is an efficient method of removing defective devices, thereby enhancing the reliability of finished semiconductor devices.
Conventionally, when a screening test of DRAMs is performed, an address signal supplied from outside of the DRAM is scanned and input to an address signal terminal of each individual DRAM which is packaged, and the word lines of the DRAM are accessed in sequence. Using this method, however, a number of input terminals are required in the DRAM in order to perform the screening test, and an address signal generator has to be provided alongside the screening apparatus.
The inventors of the present invention have proposed a semiconductor memory device wherein voltage stress can be applied simultaneously to all of the word lines, or to a larger number of the word lines than that selected in a normal operation mode. This semiconductor memory device is disclosed in U.S. patent application Ser. No. 544,614 filed Jun. 27, 1990.
The semiconductor memory device proposed by the inventors greatly improves the efficiency of screening tests of transfer gates of memory cells. When the semiconductor memory device is in the form of a wafer, memory chip regions of the wafer can be screened in a short period of time by means of a prober and a probe card and, in this case, a number of probe terminals (for example, needles of the probe card) are not needed.
When a screening test is carried out using the above-described conventional method, probe terminals are brought into contact with address signal pads on DRAM chip regions on a wafer to scan the address signals supplied from outside of the DRAM and access the word lines of the DRAMs in sequence. From the point of view of screening efficiency, it is desirable that the probe terminals be simultaneously placed in contact with the address signal pads of as many DRAM chip regions on the wafer as possible (ideally, the pads on all the DRAM chip regions). However, in this case, a large number of probe terminals are required, it is difficult to attain such a probe card, and an address signal generator must be provided alongside the prober.